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MC10H640, MC100H640 68030/040 PECL to TTL Clock Driver
Description
The MC10H/100H640 generates the necessary clocks for the 68030, 68040 and similar microprocessors. It is guaranteed to meet the clock specifications required by the 68030 and 68040 in terms of part-to-part skew, within-part skew and also duty cycle skew. The user has a choice of using either TTL or PECL (ECL referenced to +5.0 V) for the input clock. TTL clocks are typically used in present MPU systems. However, as clock speeds increase to 50 MHz and beyond, the inherent superiority of ECL (particularly differential ECL) as a means of clock signal distribution becomes increasingly evident. The H640 also uses differential PECL internally to achieve its superior skew characteristic. The H640 includes divide-by-two and divide-by-four stages, both to achieve the necessary duty cycle skew and to generate MPU clocks as required. A typical 50 MHz processor application would use an input clock running at 100 MHz, thus obtaining output clocks at 50 MHz and 25 MHz (see Logic Diagram).
Features
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PLCC-28 FN SUFFIX CASE 776
MARKING DIAGRAM*
1
* * * * * * *
Generates Clocks for 68030/040 Meets 030/040 Skew Requirements TTL or PECL Input Clock Extra TTL and PECL Power/Ground Pins Asynchronous Reset Single +5.0 V Supply Pb-Free Packages are Available*
MCxxxH640G AWLYYWW
Function
Reset (R): LOW on RESET forces all Q outputs LOW and all Q outputs HIGH. Power-Up: The device is designed to have the POS edges of the / 2 and / 4 outputs synchronized at power up. Select (SEL): LOW selects the ECL input source (DE/DE). HIGH selects the TTL input source (DT). The H640 also contains circuitry to force a stable state of the ECL input differential pair, should both sides be left open. In this case, the DE side of the input is pulled LOW, and DE goes HIGH.
xxx A WL YY WW G
= 10 or 100 = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet.
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
(c) Semiconductor Components Industries, LLC, 2006
November, 2006 - Rev. 8
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Publication Order Number: MC10H640/D
MC10H640, MC100H640
TTL Outputs
VT 25 Q2 GT GT Q3 VT VT Q0 26 27 28 1 2 3 4 5 Q1 6 GT 7 GT 8 Q4 9 Q5 10 VT 11 SEL VT 24 Q1 23 GT 22 GT 21 Q0 20 VT 19 18 17 16 15 14 13 12 VBB DE DE VE R GE DT SEL Q1 Q0 Q1 Q2 MUX /2 Q3 Q0
TTL/ECL Clock Inputs
VBB DE DE DT
/4
Q4 Q5
TTL Control Inputs
R
Figure 1. Pinout: PLCC-28 (Top View) Table 1. PIN DESCRIPTION
PIN GT VT VE GE DE, DE VBB DT Qn, Qn SEL R FUNCTION TTL Ground (0 V) TTL VCC (+5.0 V) ECL VCC (+5.0 V) ECL Ground (0 V) ECL Signal Input (positive ECL) VBB Reference Output TTL Signal Input Signal Outputs (TTL) Input Select (TTL) Reset (TTL)
Figure 2. Logic Diagram
Table 2. DC CHARACTERISTICS (VT = VE = 5.0 V 5%)
0C Symbol IEE ICCH ICCL Characteristic Power Supply Current ECL TTL Condition VE Pin Total all VT pins Min Max 57 30 30 25C Min Max 57 30 30 85C Min Max 57 30 30 Unit mA mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
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MC10H640, MC100H640
Table 3. 10H PECL DC CHARACTERISTICS (VT = VE = 5.0 V 5%)
0C Symbol IINH IINL VIH1 VIL1 VBB1 Characteristic Input HIGH Current Input LOW Current Input HIGH Voltage Input LOW Voltage Output Reference Voltage VE = 5.0 V Condition Min 0.5 3.83 3.05 3.62 Max 255 4.16 3.52 3.73 Min 0.5 3.87 3.05 3.65 25C Max 175 4.19 3.52 3.75 Min 0.5 3.94 3.05 3.69 85C Max 175 4.28 3.555 3.81 Unit mA V V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 1. PECL levels are referenced to VCC and will vary 1:1 with the power supply. The values shown are for VCC = 5.0V.
Table 4. 100H PECL DC CHARACTERISTICS (VT = VE = 5.0 V 5%)
0C Symbol IINH IINL VIH2 VIL2 VBB2 Characteristic Input HIGH Current Input LOW Current Input HIGH Voltage Input LOW Voltage Output Reference Voltage VE = 5.0 V Condition Min 0.5 3.835 3.19 3.62 Max 255 4.12 3.525 3.74 Min 0.5 3.835 3.19 3.62 25C Max 175 4.12 3.525 3.74 Min 0.5 3.835 3.19 3.62 85C Max 175 4.12 3.525 3.74 Unit mA V V
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 2. PECL levels are referenced to VCC and will vary 1:1 with the power supply. The values shown are for VCC = 5.0V.
Table 5. TTL DC CHARACTERISTICS (VT = VE = 5.0 V 5%)
0C Symbol VIH VIL IIH IIL VOH VOL VIK IOS Characteristic Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Output HIGH Voltage Output LOW Voltage Input Clamp Voltage Output Short Circuit Current VIN = 2.7 V VIN = 7.0 V VIN = 0.5 V IOH = -3.0 mA IOH = -15 mA IOL = 24 mA IIN = -18 mA VOUT = 0 V -100 2.5 2.0 0.5 -1.2 -225 -100 Condition Min 2.0 Max 0.8 20 100 -0.6 2.5 2.0 0.5 -1.2 -225 -100 25C Min 2.0 Max 0.8 20 100 -0.6 2.5 2.0 0.5 -1.2 -225 85C Min 2.0 Max 0.8 20 100 -0.6 Unit V mA mA V V V mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously.
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MC10H640, MC100H640
Table 6. AC CHARACTERISTICS (VT = VE = 5.0 V 5%)
0C Symbol tPLH tPLH tskwd* tPLH tPLH tPLH tPLH tPD tR tF fmax tpw trr Characteristic Propagation Delay ECL D to Output Propagation Delay TTL D to Output Within-Device Skew Propagation Delay ECL D to Output Propagation Delay TTL D to Output Propagation Delay ECL D to Output Propagation Delay TTL D to Output Propagation Delay R to Output Output Rise/Fall Time 0.8 V to 2.0 V Maximum Input Frequency Minimum Pulse Width Reset Recovery Time All Outputs All Outputs Q4, Q5 Q0, Q1 Q0 - Q3 Condition CL = 25 pF CL = 25 pF CL = 25 pF CL = 25 pF CL = 25 pF CL = 25 pF CL = 25 pF CL = 25 pF CL = 25 pF CL = 25 pF 135 1.50 1.25 4.0 4.0 4.0 4.0 4.3 Min 4.0 4.0 Max 6.0 6.0 0.5 6.0 6.0 6.0 6.0 6.3 2.5 2.5 135 1.50 1.25 4.0 4.0 4.0 4.0 4.3 25C Min 4.0 4.0 Max 6.0 6.0 0.5 6.0 6.0 6.0 6.0 6.3 2.5 2.5 135 1.50 1.25 4.2 4.3 4.2 4.3 5.0 85C Min 4.2 4.3 Max 6.2 6.3 0.5 6.2 6.3 6.2 6.3 7.0 2.5 2.5 Unit ns ns ns ns ns ns ns ns ns MHz ns ns
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 3. Within-Device Skew defined as identical transitions on similar paths through a device.
Table 7. VCC and CL RANGES TO MEET DUTY CYCLE REQUIREMENTS
(0C TA 85C Output Duty Cycle Measured Relative to 1.5 V) Symbol Characteristic Range of VCC and CL to meet minimum pulse width (HIGH or LOW) = 11.5 ns at fout 40 MHz Range of VCC and CL to meet minimum pulse width (HIGH or LOW) = 9.5 ns at 40 < fout 50 MHz VCC CL Condition Q0 - Q3 Q0 - Q1 Min 4.75 10 Nom 5.0 Max 5.25 50 Unit V pF
VCC CL
Q0 - Q3
4.875 15
5.0
5.125 27
V pF
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MC10H640, MC100H640
10/100H640 DUTY CYCLE CONTROL To maintain a duty cycle of 5% at 50MHz, limit the load capacitance and/or power supply variation as shown in Figures 3 and 4. For a 2.5% duty cycle limit, see Figures 5 and 6. Figures 7 and 8 show duty cycle variation with temperature. Figure 9 shows typical TPD versus load. Figure 10 shows reset recovery time. Figure 11 shows output states after power up. Best duty cycle control is obtained with a single mP load and minimum line length.
11 5.25 VCC 4.75 VCC PW (ns) 10 NEGATIVE PULSE WIDTH (ns) 5 VCC 11
10 4.75 VCC 5 VCC 9 5.25 VCC
9
0
25
50
LOAD (pF)
75
85
0
25
50 LOAD (pF)
75
85
Figure 3. Positive Pulse Width at 25C Ambient and 50 MHz Out
11 NEGATIVE PULSE WIDTH (ns) POSITIVE PULSE WIDTH (ns) 5.125 VCC 5 VCC 4.875 VCC 10 11
Figure 4. Negative Pulse Width at 25C Ambient and 50 MHz Out
10 4.875 VCC 5 VCC 5.125 VCC
9
9
0
25
50 LOAD (pF)
75
85
0
25
50 LOAD (pF)
75
85
Figure 5. Positive Pulse Width at 25C Ambient at 50 MHz Out
11 NEGATIVE PULSE WIDTH (ns) POSITIVE PULSE WIDTH (ns) 50 pF 25 pF 10 11
Figure 6. Negative Pulse Width at 25C Ambient at 50 MHz Out
10 pF
10
25 pF
10 pF 9
9
0
25
50 TEMPERATURE (C)
75
85
0
25
50 TEMPERATURE (C)
75
85
Figure 7. Temperature versus Positive Pulse Width for 100H640 at 50 MHz and VCC = +5.0 V
Figure 8. Temperature versus Negative Pulse Width for MC100H640 @ 50 MHz and VCC = +5.0 V
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MC10H640, MC100H640
6.2
4.75 V
6.0 t PD (ns) 5.8 5.6 5.4 5.2
5V 5.25 V
0
25
50 CLOAD (pF)
75
85
Figure 9. tPD versus Load Typical at TA = 25C
DT RESET, R Rtpw Q0, Q1, Q2, Q3 Rtrec
Q0, Q1
Q4, Q5
Figure 10. MC10H/100H640 Clock Phase and Reset Recovery Time After Reset Pulse
Din
Q0 Q3 Q1 Q2
Q4 & Q5 AFTER POWER UP OUTPUTS Q4 & Q5 WILL SYNC WITH POSITIVE EDGES OF Din & Q0 Q3 & NEGATIVE EDGES OF Q0 & Q1
Figure 11. Output Timing Diagram
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MC10H640, MC100H640
ORDERING INFORMATION
Device MC10H640FN MC10H640FNG MC10H640FNR2 MC10H640FNR2G MC100H640FN MC100H640FNG MC100H640FNR2 MC100H640FNR2G Package PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) PLCC-28 PLCC-28 (Pb-Free) Shipping 37 Units / Rail 37 Units / Rail 500 / Tape & Reel 500 / Tape & Reel 37 Units / Rail 37 Units / Rail 500 / Tape & Reel 500 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1672/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC10H640, MC100H640
PACKAGE DIMENSIONS
PLCC-28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776-02 ISSUE E
Y BRK D Z -L- -M- B 0.007 (0.180) U
M
T L-M
M
S
N
S S
-N-
0.007 (0.180)
T L-M
N
S
W
28 1
D
V
X VIEW D-D
G1
0.010 (0.250)
S
T L-M
S
N
S
A Z R E G G1 0.010 (0.250)
S
0.007 (0.180) 0.007 (0.180)
M M
T L-M T L-M
S S
N N
S S
H
0.007 (0.180)
M
T L-M
S
N
S
C
K1 0.004 (0.100) -T- SEATING
PLANE
J
K F VIEW S 0.007 (0.180)
M
VIEW S T L-M
S
T L-M
S
N
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --- 0.025 --- 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 --- 0.020 2_ 10_ 0.410 0.430 0.040 ---
MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --- 0.64 --- 11.43 11.58 11.43 11.58 1.07 1.21 1.07 1.21 1.07 1.42 --- 0.50 2_ 10_ 10.42 10.92 1.02 ---
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MC10H640, MC100H640
ECLinPS is a trademark of Semiconductor Components Industries, LLC (SCILLC). MECL 10H is a trademark of Motorola, Inc.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
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MC10H640/D

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